![]() |
![]() |
VLSI LabVLSI Labs manufactured by us are worldwide famous due to their reliability and capability of proving itself at all parameters of quality and technology. Our VLSI Lab include VHDL Studio, VHDK Studio with direct VHDL and VPL-FPGA-DLL-II. We invite all of you to have a fare deal for best quality products with us. LIST OF EXPERIMENTS FOR VLSI DESIGN LAB Combinational Design Exercises Design of Gates Design of AND gate Design of OR gate Design of XOR gate Design of XOR gate using other basic gates Design of 2:1 Mux using other basic gates Design of 2 to 4 Decoder Design of Half-Adder, Full Adder, Half Substractor, Full Substractor Design of 3:8 Decodre Design of 8:3 Priority Encoder Design of 4 Bit Binary to Grey code Converter Design of 4 Bit Binary to BCD Converter using sequential statement Design an 8 Bit parity generator ( with for loop and Generic statements) Design of 2,s Complementer for 8-bit Binary number using Generate statements Sequential Design Exercises Design of all type of Flip-Flops using ( if-then-else) Sequential Constructs Design of 8-Bit Shift Register with shift Right, Rhisft Left, Load and Synchronous reset. Design of Synchronous 8-bit Johnson Counter. Design of Synchronous 8-Bit universal shift register ( parallel-in, parallel-out) with 3- state output -(IC 74299) Design of 4 Bit Binary to BCD Converter using sequential statement. Design 1. Mod 3 Counter 2. Mod 5 Counter 3. Mod 7 Counter 4. Mod 8 Counter 5. Mod 16 counter 6. 4 Bit Johnson counter Design a decimal up/down counter that counts up from 00 to 99 or down from 99 to 00. Design 3-line to 8-line decoder with address latch Design of ALU 55 Lab Project/Case Studies: 2 Nos. |